graphene
Full Member level 2
Hallo,
I am using Xilinx ISE to program my FPGA using VHDL.
When I compile and synthesise a code despite ensuring its syntax and logic correctness, the synthesiser comes out with a warning which tells "WARNING:Xst:647 - Input <clk> is never used." and so on for all inputs involved.
I am very sure that the input signals are used in the sensitivity list of my process and its statements. Also ignoring the warning when I see the RTL schematic or the technology schematic, I just find the block with inpputs,outputs floated. I cleaned up my project files, again no use.
I am including my code below. Perhaps, the same warning came eve for the simplest D-flipflop a couple of days ago but now now.
I googled and read several forums but I am unable to understand it.
My question is not about how to deal with a warning but rather an error that is shown as a warning.
Please let me know your suggestions and recommendations.
LG
I am using Xilinx ISE to program my FPGA using VHDL.
When I compile and synthesise a code despite ensuring its syntax and logic correctness, the synthesiser comes out with a warning which tells "WARNING:Xst:647 - Input <clk> is never used." and so on for all inputs involved.
I am very sure that the input signals are used in the sensitivity list of my process and its statements. Also ignoring the warning when I see the RTL schematic or the technology schematic, I just find the block with inpputs,outputs floated. I cleaned up my project files, again no use.
I am including my code below. Perhaps, the same warning came eve for the simplest D-flipflop a couple of days ago but now now.
I googled and read several forums but I am unable to understand it.
My question is not about how to deal with a warning but rather an error that is shown as a warning.
Please let me know your suggestions and recommendations.
LG
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE. STD_LOGIC_ARITH.all;
----
entity mit_nasa is
port(
clk : in std_logic;
fsm_in : in std_logic;
rst : in std_logic;
fsm_out : out std_logic_vector (1 downto 0)
);
end mit_nasa;
architecture arc_mit_nasa of mit_nasa is
type state_type is (ST0,ST1);
signal present_state, next_state: state_type;
begin
rst_proc: process (clk, rst, next_state)
begin
if (rst='1') then
present_state <= ST0;
elsif (rising_edge(clk)) then
present_state <= next_state;
end if;
end process rst_proc;
comb_process: process (present_state, fsm_in)
begin
fsm_out<="00";
case present_state is
when ST0=>
fsm_out<="00";
if fsm_in<='1' then next_state<=ST1;
else next_state<=ST0;
end if;
when ST1 =>
fsm_out<="00";
if fsm_in<='1' then next_state<=ST0;
else next_state<=ST1;
end if;
when others =>
fsm_out<="00";
next_state<=ST0;
end case;
end process comb_process;
end arc_mit_nasa;