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"gated clock" warning, what is the solution for my code?

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Fractional-N

Fractional-N

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hi,
this is my code
Code VHDL - [expand]
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OUTDATA : PROCESS(sSELECT,sDATA1,sDATA2,sDATA3,sDATA4,sDATA5,sDATA6)
 BEGIN
    if (sSELECT = "000") then
        pDATAOUT <= sDATA1;
      elsif (sSELECT = "001") then
        pDATAOUT <= sDATA2;
      elsif (sSELECT = "010") then
        pDATAOUT <= sDATA3;
      elsif (sSELECT = "011") then
        pDATAOUT <= sDATA4;
      elsif (sSELECT = "100") then
        pDATAOUT <= sDATA5;
      elsif (sSELECT = "101") then
        pDATAOUT <= sDATA6;
    end if;
end process;


i get warning:
Code: 
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   Mem/Memory/pDATAOUT_not0001 is sourced by a combinatorial pin. This
   is not good design practice. Use the CE pin to control the loading of data
   into the flip-flop.

what is wrong with my code. I don't know how should i change it so that i don't have a gated clock. can you help me? any suggestions?
 

Because as you use not full sSELECT states pDATAOUT is synthesized as LATCH (need to hold previews state in case of sSELECT="11X" , so its gated by combinatorial logic) and not as MUX unit.

either add there else statement or add CLK signal. And you can remove sDATAx from sensitivy list because its only sSELECT sensitive process now.
 
Re: &quot;gated clock&quot; warning, what is the solution for my code?

The warning seems to miss the problem. I presume you want to make a pure combinatorial MUX but you generate a latch because select isn't fully decoded, pDATAOUT is hold for two input sSELECT codes.

You'll want to select a default output value and code it respectively.

- - - Updated - - -

P.S.: A mux can be coded as selected assignment in concurrent code, without a process.
 
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