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need help in multiplexer in FPGA

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dil01

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i need help understanding this verilog code..

in this code first 2X1 multiplexer is made using gate level model..

then they have used the instance of 2X1 mux to create 4X1 multiplexer..

i dont understand how they have used 2x1 mux in 4x1 generation and then used 2x1 and 4x1 mux to generate 8x1 multiplexer..

can someone plz help and make me understand the code..


Code starts from here

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module 2-1mux(x,b,a,s);
input a,b,s;
output x;
wire w1,w2,w3;
not(w1,s);
and(w2,w1,a);
and(w3,s,b);
or(x,w2,w3);
endmodule
module 4-1mux(x,data,sel);
input [3:0] data;
input [1:0] sel;
output x;
2-1mux ins1(w1,data[3],data[2],sel[1]);
2-1mux ins2(w2,data[1],data[0],sel[1]);
2-1mux ins3(x,w1,w2,sel[0]);
 
endmodule
module 8-1mux(x,data,sel);
input [7:0] data;
input [2:0] sel;
output x;
4-1mux ins1(w1,data[7:4],sel[2:1]);
4-1mux ins2(w2,data[3:0],sel[2:1]);
2-1mux ins3(x,w1,w2,sel[0]);
 
endmodule
 
Last edited by a moderator:

Who ever wrote that code you're reviewing isn't very experience using Verilog. They have an invalid name for their modules, they aren't using 2001 port declarations, and they aren't instantiating with named port mapping.

Maybe showing you the behavioral description will make it easier to see.
Code Verilog - [expand]
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module mux_4to1(
  output        x,
  input   [3:0] data,
  input   [1:0] sel
);
 
  wire d_3to2, d_1to0;
 
  always @ * begin
 
    case (sel[1])  // 2-to-1 mux
      1'b0 : d_1to0 = data[0];
      1'b1 : d_1to0 = data[1];
    endcase
 
    case (sel[1])  // 2-to-1 mux
      1'b0 : d_3to2 = data[2];
      1'b1 : d_3to2 = data[3];
    endcase
 
  end
 
  // select between the 2-to-1 muxes
  assign x = sel[0] ? d_3to2 : d_1to0;
 
endmodule
 
 
module mux_8to1 (x
  output        x,
  input   [7:0] data,
  input   [2:0] sel
);
 
  always @ * begin
 
    case (sel[2:1])  // 4-to-1 mux
      2'b00 : d_3to0 = data[0];
      2'b01 : d_3to0 = data[1];
      2'b10 : d_3to0 = data[2];
      2'b11 : d_3to0 = data[3];
    endcase
 
    case (sel[2:1])  // 4-to-1 mux
      2'b00 : d_7to4 = data[4];
      2'b01 : d_7to4 = data[5];
      2'b10 : d_7to4 = data[6];
      2'b11 : d_7to4 = data[7];
    endcase
 
  end
 
  // select between the two 4-to-1 muxes
  assign x = sel[0] ? d_7to4 : d_3to0;
 
endmodule
 

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