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24th January 2005, 11:53 #1
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SS, TT, FF corner
Can anyone explain what are the main differences between the three corners (SS,TT and FF) and why the worst case is SS with 0.9Vdd @ 130°C and best case is FF with 1.1 Vdd @ 30°C.
Thanks

24th January 2005, 12:21 #2
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Re: SS, TT, FF corner
Best case means higher speed. Delay of CMOS gates became smaller speed higher. The same behavior of CMOS gates can cause:
Higher VCC
Lower temperature
Lower threshold voltages of NMOS and PMOS transistors.
So that's why the best case is HIGH VCC, LOW TEMPERATURE and LOW PMOS/NMOS threshold voltage (FF). And worst case is just vice versa.
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25th January 2005, 04:19 #3
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Re: SS, TT, FF corner
the electronic's speed

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26th January 2005, 02:18 #4
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Re: SS, TT, FF corner
Corners are usualy calculated as +/ 3 sigma values of Typical. What you indicate are simulation conditions not the SS/TT/FF spice model corners.

26th January 2005, 09:00 #5
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Re: SS, TT, FF corner
SS: NMOS slow, PMOS slow
FF: NMOS fast, PMOS fast
TT: NMOS typical, PMOS typical

27th January 2005, 05:32 #6
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Re: SS, TT, FF corner
This is not always ture. Sometimes the worst case happens at fast NMOS, slow PMOS, and so on.
Originally Posted by ccw27

27th January 2005, 07:05 #7
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Re: SS, TT, FF corner
Process corner simulation:
Generally,ff is the worst corner for ADC and VCO.
ss becomes worst in some cases such as logic circuits.

28th January 2005, 02:32 #8
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Re: SS, TT, FF corner
variation in channel length

28th January 2005, 13:42 #9
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Re: SS, TT, FF corner
Originally Posted by Teddy

28th January 2005, 14:32 #10
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Re: SS, TT, FF corner
Originally Posted by lakeoffire

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31st January 2005, 03:32 #11
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Re: SS, TT, FF corner
Originally Posted by cretu

1st February 2005, 10:02 #12
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Re: SS, TT, FF corner
For resistor variation (min, typ, max), do you typically associate ss corner with max and ff with min or do you simulate with all possible permutation?
Thanks

2nd February 2005, 08:33 #13
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Re: SS, TT, FF corner
The whole point of simulating something at SS is to see worst case delay.
But in case the circuits or design has some race condition then in that case worst case delay can also be visible by the crosscorner analysis.
Regarding sigma point can anybody explain which sigma(current, threshold voltage etc) actually we are talking about ?

2nd February 2005, 16:07 #14jiangwpGuest
Re: SS, TT, FF corner
The nature of semiconductor material is so.
You can refer to the semiconductor device physical.

3rd February 2005, 04:28 #15
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Re: SS, TT, FF corner
The head room plays a part in what the worst case combinations is, although it's always at low VCC.

3rd February 2005, 07:25 #16
SS, TT, FF corner
hi, zmliu, could you explain why ff is the worst corner for ADC and VCO?

6th February 2005, 12:09 #17
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Re: SS, TT, FF corner
Worst Case corners in the foundry side is just referred to several extreme cases of the various process parameters (e.g. ff, ss of MOSFET). All ff, ss, sf, fs are called worst cast corners in the MOSFET.
However in the user and designer sense worst case corner is referred to the combinations of corners that leads to the most worst case performance situation, and depends on what performance the user is interested to, the same corner combination can be best case or worst case.
For example, ff corners in the mosfet can be the best case corner in terms of speed (e.g. GBW) specification, but also can be the worst case corners in terms of stability (e.g. phase margin) spec. Hope this help.

11th February 2005, 15:46 #18
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Re: SS, TT, FF corner
Most importantly, the corners of a process are designated by five parameters
1. Mobility variation due to implantation of N+ and P+
2. Vth variation
3. Resistance of the actives
4. Body coefficient
5. Oxide thickness
Other parameters like the effective Length, effective width, Cjsw caps, Cj caps also change. Hence Slow Slow, Fast Fast corners come into picture

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11th February 2005, 17:02 #19
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Re: SS, TT, FF corner
Originally Posted by Vamsi Mocherla

15th February 2005, 07:42 #20
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Re: SS, TT, FF corner
Weak nmos,Weak Pmos and high temperature worst corner in terms of speed (Vt is more ,currents are less ,drive is less ,very high temp mobility degrades ).
Fast nmos,Fast pmos and low temp is the best corner
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