hi

I'm new in the VHDL world..

I'm writing a VHDL code that do some image processing (image warping).in need to read the image from some RAM.the image is in gray scale(each pixel is an 8bit).

i have a VHDL model that read from external DRAM( i didn't write this model) a 1 line of DRAM and write it to a RAM in my FPGA each time i tell him that i finished to process the data in the internal ram.
my code need an access to each pixel (8bit-cell) in each clock cycle because of that im working with internal RAM.
im working this way someone told me that if i want to read only 1 cell(8bit) from external DRAM It takes longer(few clock cycles) than reading an entire row from DRAM.

Is it true?
Can anyone tell me the difference in terms of clock cycles between cell reading and line reading from DRAM?


(
thanks