Automatic Layout Synthesis from Schematic Netlist Possible?

I am implementing a custom multiplier utilizing Data Driven Dynamic Logic. I have constructed both the schematic and layout. The post-layout delay is about 30x greater than the pre-layout delay times. I know there should be somewhat of a discrepancy between pre- and post- layout delay times, but I do not think it should be this great.

Since there is no standard library for this type of logic I hand did all placement and routing of the design, making it not optimized for cell placement, routing, or wire thickness.

Is there a way to take the schematic netlist and automatically synthesis an optimized layout using my own set of layout cells?

Or a way to take my pre-existing layout and have it redo the placement and routing?

I know the process of automatically synthesizing layout from an HDL but unsure of the workflow to do it from a schematic. Any input would be beneficial, thanks in advanced!

Looks like you may want to use the Constraint-Driven Layout Tool from Cadence. Here's the datasheet
https://www.cadence.com/rl/Resources/datasheets/virtuoso_vlsXL_ds.pdf

I don't think its completely automated, but A semi-guided methodology that allows Analog designers to quickly slap down caps and inductors and to build analog building blocks. Most of the work is done to perform tune the components from there.

Cheers!
Mike