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Xilinx not synthesizing- taking long time

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win2010

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Hi,
I`m working with too many signals and variable(VHDL), while synthesizing it taking long time and also not completing.

Ex: signal Buf1(64799 downto 0);
signal Buf2(64799 downto 0);

What is the alternative to this problem and how to design such complected buffers..


Thank you..
Vinayak
 

Are you deliberatly trying to have so many registers, or did you intend for these signals to infered memories?
Massive arrays that create registers will always take a long time to compile.

If you did intend to have a massive register array - why?
 

I`m designing interleaver so need to store 64800 bits and also do circular shift using formula and output those values bit by bit....
 

That still doesnt really explain anything - why cant you use a memory?
 

If i go for memory(RAM) then complexity increases and also delay increases....

Is their any effective solution for this...?
 

Yes - increase complexity and delay.
It sound like you dont really understand FPGA architecture. What is wrong with a longer pipeline delay?
 

I`m beginner not so much good at coding.. Now trying to understand things. Really i face difficultly with using RAM so only asked.

Thank you for kind reply...
 

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