Script to find the Source Flip-Flops and the destination Flip Flops with path

How to find the Source Flip-Flops and the Destination Flip Flops with path

Hi All,

Is there any way to find the Source Flip Flops and the Destination Flip Flops with full path in our ASIC RTL Design.
For giving constraints in my design I need to find the Source Flip Flops which are in CLK_1 clock domain
to the Destination Flip Flops which are in CLK_2 domain.

For example if there are Flip Flops like A1_FF, B1_FF and C1_FF in CLK_1 domain and X2_FF and Y2_FF in CLK_2 domain.
If the combination of A1_FF and B1_FF result D1 signal, and the D1 is driven to the X2_FF
also the combination of B1_FF and C1_FF result E1 signal, and the E1 is driven to the Y2_FF.

Then I need to find the A1_FF and B1_FF as Source Flip Flops for Destination Flip Flop X2_FF,
also B1_FF and C1_FF as source Flip Flops for Destination Flip Flop Y2_FF.

Please let me know is there any script or command to fine the same instead of searching the entire RTL design.

If you used a Clock Domain Crossing tool, it will check every path going from one clock domain to anothe one, I expect it could report the clock mixing stuff.
If you have done a synthesis of your code, you could report paths from all path from one clock domain to all flops of the others clock domain.