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  1. #1
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    How to give false path constraints in Vivado *.xdc file for a group of signals ?

    Hi All,

    I am using Xilinx's Vivado 2013.3 for generating the *.bin file.
    There are a lot asynchronous paths in my design.
    for example if I have grouped the signals like :
    # in CLK1 domain
    set GROUP1 [get_cells {sig_a1}];
    set GROUP1 [get_cells {sig_a2}];
    set GROUP1 [get_cells {sig_a3}];

    # in CLK2 domain
    set GROUP2 [get_cells {sig_b1}];
    set GROUP2 [get_cells {sig_b2}];
    set GROUP2 [get_cells {sig_b3}];


    here the sig_a1 in CLK1 domain driven to sig_b1 in CLK2 domain. Similarly sig_a2 to sig_b2 and sig_a3 to sig_b3.

    How we can give the false path here in *.xdc file.

    Whether we need to use set_clock_groups or set_false_path in this situation ?
    Thanks & Regards,
    Shibin Bose Kavara

    " Take chances, make mistakes. That's how you grow. Pain nourishes your courage. You have to fail in order to practice being brave "

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  2. #2
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    Re: How to give false path constraints in Vivado *.xdc file for a group of signals ?

    Something like this should do the trick: set_clock_groups -asynchronous -group GROUP1 -group GROUP2

    You can look at AR# 44651 for more information

    Regards



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