TON2
Newbie level 2
Large array in VHDL , too much resources required
Hi,
In 1 clock cycle, my design output
output_real : out std_logic_VECTOR(15 downto 0);
I have to run my design for 2048x64 clk and store all the 2048x64 output_real to be used later.
Problem is I tried to store the whole output in a "Signal" format ( array of size [2048][64][16] )but it is too large, are there any alternative solutions?
I'm thinking of writing it into a table but not sure how to do it.
Below is how I declare my output array:
type N2048_16 is array( 0 to 2047) of std_logic_vector( 15 downto 0 );
type 64Channel_N2048_16 is array( 0 to 63) of N2048_16;
Thanks in advance for advice!
Hi,
In 1 clock cycle, my design output
output_real : out std_logic_VECTOR(15 downto 0);
I have to run my design for 2048x64 clk and store all the 2048x64 output_real to be used later.
Problem is I tried to store the whole output in a "Signal" format ( array of size [2048][64][16] )but it is too large, are there any alternative solutions?
I'm thinking of writing it into a table but not sure how to do it.
Below is how I declare my output array:
type N2048_16 is array( 0 to 2047) of std_logic_vector( 15 downto 0 );
type 64Channel_N2048_16 is array( 0 to 63) of N2048_16;
Thanks in advance for advice!