Solace
Newbie level 3
Hello!
I have an unusual task: i need to synthesis scheme with extended capacitance on wires. In other words, i need to compile design with annotated capacitance to all wires in design. Like, as i using maxed area wireload model instead of actual wldm. The problem is: my library doesn't support wldm at all. It can only be used in -topology mode of DC, or with zero-delay wldm in normal mode.
So, what we have.
1. set_load - works on ports and wires. The problem is - this command works only on fixed (irremovable) nets and ports. After the compilation any internal nets with annotated delay through set_load are gone. So, this command works only on inputs, outputs and set_dont_touch nets. I cant use set_dont_touch bcs i need to compile project with all set of options including optimization. I cant even use compile_ultra with -incremental key, bcs i really need a full compilation.
2. what else? I don't know
So, the question is:
What can i do, to annotate capacitance, that doesn't really exist, and make a full compilation? All new wires must have this annotation, so DC cannot just replace annotated wire with not annotated to achieve a better performance.
Another idea is - to increase all target library cells output pin capacity. Manually, by editing .lib file. Bcs i don't know how to do it with DC commands. After the compilation i can simply change target library back. I don't like this method. Any other ideas?
Thanx!
I have an unusual task: i need to synthesis scheme with extended capacitance on wires. In other words, i need to compile design with annotated capacitance to all wires in design. Like, as i using maxed area wireload model instead of actual wldm. The problem is: my library doesn't support wldm at all. It can only be used in -topology mode of DC, or with zero-delay wldm in normal mode.
So, what we have.
1. set_load - works on ports and wires. The problem is - this command works only on fixed (irremovable) nets and ports. After the compilation any internal nets with annotated delay through set_load are gone. So, this command works only on inputs, outputs and set_dont_touch nets. I cant use set_dont_touch bcs i need to compile project with all set of options including optimization. I cant even use compile_ultra with -incremental key, bcs i really need a full compilation.
2. what else? I don't know
So, the question is:
What can i do, to annotate capacitance, that doesn't really exist, and make a full compilation? All new wires must have this annotation, so DC cannot just replace annotated wire with not annotated to achieve a better performance.
Another idea is - to increase all target library cells output pin capacity. Manually, by editing .lib file. Bcs i don't know how to do it with DC commands. After the compilation i can simply change target library back. I don't like this method. Any other ideas?
Thanx!