Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] basic query on gate array, structured asics and standard cell asics

Status
Not open for further replies.
E

emmagood

Member level 4
Joined
Feb 13, 2010
Messages
72
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
1,825
Hello,

I was going through asics and have a basic query pls.

If have understood correctly, in standard cell asics, the logic is implemented using pre available cells and then the ic is fabricated.
In case of gate array and structured asics there are pre-fabricated ics with array of tiles in them (containing basic components) and they are to be configured by user as per the requirement.

Is this correct. IF so, how are gate array and structured asics programmed.

Thanks,
Emma Good
 

With gate arrays the processing is stopped before final metal layers and the wafers stored. The final metal layers are added later to suit the customers requirements.

Keith
 
OK... and what about structured asics..
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top