TonyLS
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There's a sub-block in my design that I receive from another group which has two test ports tied to 1'b0. Within my scan insertion script (using test compiler within dc_compiler) which uses the ddc, how can I change the 1'b0 to 1'b1.
I know I can go back to synthesis and change the RTL to the 1'b1 value but I would like to do it within the test insertion flow instead of the synthesis flow.
The reason why these signals are not brought to the top level is that our semi vendor can some how deal with it at the sub-module level.
Thanks for your help.
I know I can go back to synthesis and change the RTL to the 1'b1 value but I would like to do it within the test insertion flow instead of the synthesis flow.
The reason why these signals are not brought to the top level is that our semi vendor can some how deal with it at the sub-module level.
Thanks for your help.