Nidhi gupta
Newbie level 1
Synthesis using altera
My design consists of many FSMs interacting with each other.What factors we should consider while writing vhdl code for Altera devices so as to optimise the design
also, is it possible to use vhdl testbench file instead of scf file.
EDA E-books Upload/Download is not a place for such discussions. Read the rules and obey, or you will be warned and eventually banned. Post in the correct forum. Topic moved.
/pisoiu
My design consists of many FSMs interacting with each other.What factors we should consider while writing vhdl code for Altera devices so as to optimise the design
also, is it possible to use vhdl testbench file instead of scf file.
EDA E-books Upload/Download is not a place for such discussions. Read the rules and obey, or you will be warned and eventually banned. Post in the correct forum. Topic moved.
/pisoiu