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Effects of flop's hold time problems

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corgan

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Hold time quesiton..

If a flop has hold time problem, then it will become metastable.
And the voltage level of Q(output) of the flop couldn't be determinate.

Is the above statement correct?
 

Hold time quesiton..

not exactly.

The metastability is caused by a small timing window around the clock edge.

If hold time violation happens, the output value goes to unknown/arbitrary value typically.
 

Re: Hold time quesiton..

in simulation, if a dff have hold violation, the Q should be X state ( unknow state).
but in real chip, the Q should be low voltage or high voltage, but can not be determine low or how. also said, no X state in real chip, it only occure in simulation.
 

Re: Hold time quesiton..

hold time is basically time req by a data toremain stable, after valid clk edge ,
metastability will also caused by set up violation
 

Re: Hold time quesiton..

how can i eliminate hold time warnnings issued by the EDA tools? Thanks.
 

Re: Hold time quesiton..

yes, what you said is right. If a flop has hold time problem, then it will become

metastable.And the voltage level of Q(output) of the flop couldn't be determinate.



corgan said:
If a flop has hold time problem, then it will become metastable.
And the voltage level of Q(output) of the flop couldn't be determinate.

Is the above statement correct?
Click to expand...
 

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