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Help on DRC Error: N+SD to Psub tap spacing must be <= 10.0 um

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anwarkb555

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Hi,

I am new to Cadance analog design flow. I am trying to buid a CMOS common source apmlifier. Library used is gdpk180nm. I have sussessfully built the circuit in Virtuoso Schematic editor and simulated it in ADE XL. When we try to do layout in Virtuoso Layout Suite, it is giving a DRC error "N+SD to Psub tap spacing must be <= 10.0 um". Assura DRC marks two locations with this error. Marked locations are the top region of source and drain of NMOS transistor. Not able to get any clue on this. Please help.

Thanks
Anwar
 

Actually this error message is rather self-explaining: you need a p+ diffusion area ("Psub tap") close (<= 10.0 um) to the n+ source (and drain) areas of the NMOS. Connect this Psub tap via contact and metal_1 to GND (like your NMOS source, probably). See e.g. this inverter layout from a Cādence tutorial:
Tutorials-Cadence-ExLayout-Inv-004.png
 
Dear erikl,

Thank you for your valuable help. That soilved the error. I was not able to understand the terminology. My mistake. Thank you very much for the help.

And do you have any reference document for these kind of common errors?

Thanks and regards
Anwar
 

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