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    How to minimize timing score in Xilinx ISE

    Deal all,
    I m getting high timing score for two clk nets in Xilinx ISE, how to minimize timing score or make it zero.
    Can any one explain step by step.
    Thanks
    "Doubt grows with knowledge."
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    Re: How to minimize timing score in Xilinx ISE

    moreinfoplzkthxbye ^^

    Or to be more verbose ... could you give us a bit more information? This is rather generic. Can you copy/paste the timing report and tell us what the offending nets are?



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    Re: How to minimize timing score in Xilinx ISE

    Could you post the constraints in the UCF files as well as the Timing errors that you are getting. It would be good if you could also tell us what synthesis and PNR options you are using the ISE Tool.



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    Re: How to minimize timing score in Xilinx ISE

    Have you tried smartxplorer to see how bad things are?

    If none of the smartxplorer runs meet timing you will likely have to rewrite some of your RTL to correct large cones of logic between registers. You can look at all the timing reports of each smartxplorer run to determine the most egregious paths.

    Note: Some designs might actually produce logic that is different than the RTL when using the "logic optimization" switch. I had a design that would actually be severely broken when that switch was enabled, and the problem wasn't in the same location when changes were made. Try debugging a moving target when you don't realize it's the tool that is doing it!

    Regards



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    Re: How to minimize timing score in Xilinx ISE

    Quote Originally Posted by ads-ee View Post
    Have you tried smartxplorer to see how bad things are?

    If none of the smartxplorer runs meet timing you will likely have to rewrite some of your RTL to correct large cones of logic between registers. You can look at all the timing reports of each smartxplorer run to determine the most egregious paths.
    Hey, not a bad idea. I've never done that in this sort of case. Or rather, what I think is probably this sort of case. Because it's more likely it's just a bad design, and back to the drawing board.

    But ... have you had an instance where your design was okay, then you got crap timing results. And then you thought, naaaah my code is awesome, the tools must be crap. Run smartxploder, and voila, you get some crap timing and some great timings. See! You knew it was those silly synthesis settings.

    If yes, then: really? What kind of circuit was that, and what did ISE do to your design with default settings?

    PS: All the cases where I've used smartxplorer was where I knew I was already asking for a little too much. But hey, engineer, so I want the last bit of performance that's to be had!



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    Re: How to minimize timing score in Xilinx ISE

    Quote Originally Posted by mrflibble View Post
    Hey, not a bad idea. I've never done that in this sort of case. Or rather, what I think is probably this sort of case. Because it's more likely it's just a bad design, and back to the drawing board.

    But ... have you had an instance where your design was okay, then you got crap timing results. And then you thought, naaaah my code is awesome, the tools must be crap. Run smartxploder, and voila, you get some crap timing and some great timings. See! You knew it was those silly synthesis settings.

    If yes, then: really? What kind of circuit was that, and what did ISE do to your design with default settings?

    PS: All the cases where I've used smartxplorer was where I knew I was already asking for a little too much. But hey, engineer, so I want the last bit of performance that's to be had!
    I've seen instances where my designs would after running smartxplorer produced both 2000+ timing scores for a couple of the strategies and 0 for the rest. I've found that the various strategies really affect the initial placement (especially for those designs where you are pushing the maximum usable clock frequencies and utilizations). From what I've experienced once you have a good placement of the design you can lock down the BRAMs and DSPs and pretty much any of the smartxplorer runs would have 0 timing scores.

    Of course YMMV as I've normally had to deal with designs with 10+ clock domains (asynchronous to each other), extremely large number of control sets, 70%+ BRAMs used, and 90%+ of the IO used and locked down BEFORE the first time I've done place and route on the design .

    And some of those circuits that your questioning me about were simple 5-input operations (1 LUT) feeding a register in the same SLICE, but placement put the 5 input on the other side of the die . I've noticed the harder you push Xilinx or Altera tools the more likely simple logic like that gets completely placed incorrectly when the place and route tools try to make timing somewhere else, because of it's bad placement decisions.

    Regards



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    Re: How to minimize timing score in Xilinx ISE

    Quote Originally Posted by ads-ee View Post
    And some of those circuits that your questioning me about were simple 5-input operations (1 LUT) feeding a register in the same SLICE, but placement put the 5 input on the other side of the die . I've noticed the harder you push Xilinx or Altera tools the more likely simple logic like that gets completely placed incorrectly when the place and route tools try to make timing somewhere else, because of it's bad placement decisions.
    There's also another thing that can go wrong there. If you instantiate a LUT5 (or LUT6 for that matter), and then try to connect the output to something in the same slice, things can go horribly wrong as you noticed. Check out the difference between LUT5, LUT5_D and LUT5_L. If you want to route from the output of a LUT to a FF in the same slice, then it has to have a Local Output. If it doesn't you get a fun surprise.

    I've run into a similar problem to what you describe. And although it didn't plonk the register on the other side of the die, it wasn't exactly close either. Something like 4 hops away (aka long route). That was when I used a regular LUT5. When I changed that to LUT5_L ... tada! It then had a routing resource to the FF in the same slice, and problem solved.



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    Re: How to minimize timing score in Xilinx ISE

    Quote Originally Posted by amitjagtap View Post
    Deal all,
    I m getting high timing score for two clk nets in Xilinx ISE, how to minimize timing score or make it zero.
    Can any one explain step by step.
    Thanks
    Hi,

    To minimize your timing score.. you need to synthesize your design with the correct constraints. XST takes constraints for synthesis and produces a netlist with the timing information embedded in it which is then used for Mapping and P&R.

    1. XST constraints are specified using the XCF file. for example.. design.xcf . Here you specify the clocks, clock relationships if any, false paths, multi-cycle paths, io delays .etc.

    2. In the UCF files make sure to specify all the clocks and also other delay/multi-cycle paths.

    3. Xilinx MAP and PAR tools have built-in options to do timing driven mapping and placement. Hold errors can be solved by using the -k option in PAR.

    For more options check out the Xilinx command line tools user guide.

    These tricks will help you achieve better timing score.



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