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[SOLVED] fast clock signal to slow clock signal transfer - I Need No timing check.

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Hi.
I want to pass a signal from a fast clock domain to slow clock domain but the timing analysis fails.

I need no timing analysis for this path.
How can I disable Timing analysis for these signals?
Or how can disable Timing analysis for these domains?

I'm using ISE 14.3.
 

Port Map said:
How can I disable Timing analysis for these signals?
Click to expand...

Use a TIG contraint. You can read all about TIG constraints in this here document.

Alternatively if you have more than a 1-bit signal, you may want to use a small fifo to go between clock domains.
 
Very thanks to your helps.
I use the TIG in UCF file like this:

NET "sClock20M" TNM_NET =FFS sClock20M_GRP;
NET "sClock200M" TNM_NET =FFS sClock200M_GRP;
TIMESPEC TS_Example = FROM "sClock200M_GRP" TO "sClock20M_GRP" TIG;
 

That TIMESPEC seems to be okay.
 

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