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Confused by the post place&route simulation

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mhytr

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The following is the statemachine in my design:
initialize->a1->a2->a3->a1->a2->a3->a1.............
The state is setted to "initilize" and it is supposed to change to "a1" at the next posedge clock .In the behavioral simulation it works so,but in the post-translate simulation it waits for 2 cycles(in these 2 cycles the state is "initialize") and then change to "a1" and it waits for 3 cycles in the post-place&route simulation .
Though the state machine works well except several delay cycles in the "initialize" state ,i really want to know the reason of these delay cycles.
Thanks!
 

My first thought could be, that during initialization, the condition is not at a1.

if it at a2 for example, time is needed to complete sequence to get to a1.

since I see only 3 conditions, a1 - a3 and repeat..., the delay during initialization could be because you might have multiple conditions. ie a1 and a3 might = 1.
In this case it will take extra time to reset all conditions.

I hope this explanation is clear. If not I'll try to be more clear if asked, or another kind member could explain further.

Hope this helps,
wa
 

The state stays at "initialize" in the 3 delay cycles.I think the delay cycles has sth to do with the "GSR" signal of xilinx device(defined in glbl.v),but i still can't explain why.
It seems that the state machine does not work until "glbl/GSR" signal changes from 1 to 0 .That is to say,at the negedge of "reset_n" the state is setted to "initialize" and it in not changed with the comming of posedge clock,because the "GSR" signal is still "1".After the "GSR" signal changes to "0",the system is able to acknoledge the sate is "initialize" and the state begin to change as expected with the comming of posedge clock .
 

I think you have ignored the input delay in your test bench. The p&R netlist comes with timing info. and you have to change the inputs with setup time consideration.
 

Usually, in post PAR a global reset cycle of 100 ns is inserted in the post PAR model check it out "ROC"
 

check your code, if a1---->a3 sequentially set cycle by cycle, it maybe behaviour simulation mismatch the P&R netlist. Try to modify the delay in the behavioral simulation. Good luck!
 

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