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[SOLVED] Overflow of integrator in CIC filter

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yhatagishi

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Hello all,

I am trying to make CIC filter using VHDL and will implement it on FPGA.
I could design a CIC filter with the output from comb part does not overflow, but it DOES overflow in integrator part.

From some documents and my result, I know the overflow of integrator does not influence the final output.
However, when it comes to designing the CIC filter by VHDL, the overflow of integrator becomes a big problem because of the limitation in bit width.

So is there any way to prevent or avoid the problem of the overflow in integrator??


Any helps will be appreciated.

Yukihiro Hatagishi
 

CIC uses modular arithmetic, overflow is by design. All CIC stages must have the minimal bitwidths according to CIC theory, then the output will be correct despite of integrator overflow.
 
Dear FvM,

Thank you for quick reply.

I did not (and still do not) know about modular arithmetic but I found that it works fine in vhdl (ModelSim) too.
I thought the overflow could be ignored only in high spec simulation (like Maple and MapleSim)...

Thank you very much.
I will study about modular arithmetic.

Yukihiro Hatagishi
 

You should primarly review classical CIC literature like the original Hogenauer paper.
 

Can you find information of FPGA Chip on memory maximum limit ? Simple calculation form don't have memory management for safe work .
 

Dear phongphanp,

Thanks for your reply.

I am pretty new to FPGA and I do not know what the memory mean in FPGA...
Can you give me some information or documents about the memory you mentioned please?


Best regards,
Yukihiro Hatagishi
 

The document I read is below. It gave me good ideas about CIC filter but never mentioned about modular arithemetic.
www.dspguru.com/sites/dspguru/files/cic.pdf
Thanks anyway!!
Click to expand...
The paper gives a good introduction to CIC filters. But the overflow problem isn't discussed in depth therein.

The relation of CIC to modular arithmetic is discussed in the Register Growth chapter of An economical class of digital filters for decimation and interpolation by E. B. Hogenauer. But if you're not so interested in the mathematical background, it's just a name. In simple words, it means the overflow is normal behaviour and necessary for correct operation.

It's important however to understand the bit length requirements for each CIC stage. It's discussed in many textbooks and papers. One of the best representations is still in Hogenauer's original paper.
 

Dear FvM,

Is the one below is what you have mentioned?
**broken link removed**
I will read through it.

But what I am facing right now is,
Simulation: works great
Experiment(when I downloaded the system to the FPGA) : does not work

Why does this happen?
Does the paper have the answer to this?
Or should I study about FPGA more...

Thanks,

Yukihiro Hatagishi
 

There are many ways to write non-synthesizable HDL. Show your code.
 

Dear FvM,

Thanks for your reply.

So the point is simulation is simulation and real is real??

The code is below (sorry but I do not know how to summarize the code...)
Code: 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DSADC IS -- a delta sigma analog to digital converter
	PORT (
		clock			:	IN STD_LOGIC;
		reset			:	IN STD_LOGIC;
		data_in		:	IN STD_LOGIC;
		dac_out		:	OUT STD_LOGIC; -- 1 bit out for dac
		data_out		:	OUT STD_LOGIC_VECTOR(9 DOWNTO 0) -- the result of adc
	);
END ENTITY;

ARCHITECTURE behavior OF DSADC IS

	COMPONENT OverSampler IS -- a simple flip flop
		PORT (
			clock		:	IN STD_LOGIC;
			reset		:	IN STD_LOGIC;
			data_in	:	IN STD_LOGIC;
			data_out	:	OUT STD_LOGIC
		);	
	END COMPONENT OverSampler;
	COMPONENT cic_filter IS -- the cic filter
		PORT (
			clock		:	IN STD_LOGIC;
			reset		:	IN STD_LOGIC;
			data_in	:	IN STD_LOGIC;
			data_out	:	OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
		);	
	END COMPONENT cic_filter;
	
	SIGNAL oversampled_data	:	STD_LOGIC;
	
	BEGIN
	dac_out <= oversampled_data;
	
	compOverSampler	:	OverSampler
		PORT MAP(clock, reset, data_in, oversampled_data);
	compCIC				:	cic_filter
		PORT MAP(clock, reset, oversampled_data, data_out);
		
END ARCHITECTURE behavior;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY cic_filter IS
	PORT (
		clock		:	IN STD_LOGIC;
		reset		:	IN STD_LOGIC;
		data_in	:	IN STD_LOGIC;
		data_out	:	OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
	);
END ENTITY cic_filter;

ARCHITECTURE behavior OF cic_filter IS
	COMPONENT integrator IS
		PORT (
			clock		:	IN STD_LOGIC; -- original clock
			reset		:	IN STD_LOGIC;
			bit_in	:	IN STD_LOGIC;
			data_out	:	OUT STD_LOGIC_VECTOR(9 DOWNTO 0)		
		);
	END COMPONENT integrator;
	COMPONENT decimator IS
		GENERIC (
			decimation_rate	:	INTEGER RANGE 0 TO 1023 := 500
		);
		PORT (
			clock					:	IN STD_LOGIC;
			reset					:	IN STD_LOGIC;
			data_in				:	IN STD_LOGIC_VECTOR(9 DOWNTO 0);
			decimated_clock	:	OUT STD_LOGIC;
			data_out				:	OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
		);
	END COMPONENT decimator;
	COMPONENT comb IS
		PORT (
			clock		:	IN STD_LOGIC; -- decimated clock
			reset		:	IN STD_LOGIC;
			data_in	:	IN STD_LOGIC_VECTOR(9 DOWNTO 0);
			data_out	:	OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
		);	
	END COMPONENT comb;
	
	SIGNAL int_result			:	STD_LOGIC_VECTOR(9 DOWNTO 0); -- corresponds to "data_out" of integrator and "data_in" of decimator
	SIGNAL decimated_clock	:	STD_LOGIC; -- decimated by 512, corresponds to "clock" of comb
	SIGNAL dec_result			:	STD_LOGIC_VECTOR(9 DOWNTO 0); -- corresponds to "data_out" of data_out" of decimation and "data_in" of comb
	
	BEGIN
	compIntegrator	:	integrator
		PORT MAP(clock, reset, data_in, int_result);
	compDecimator	:	decimator
		GENERIC MAP(512)
		PORT MAP(clock, reset, int_result, decimated_clock, dec_result);
	compComb			:	comb
		PORT MAP(decimated_clock, reset, dec_result, data_out);
END ARCHITECTURE behavior;

--------------------------------------------------------------------------------
-- integrator
-- works at original clock rate
--------------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY integrator IS
	PORT (
		clock		:	IN STD_LOGIC; -- original clock
		reset		:	IN STD_LOGIC;
		bit_in	:	IN STD_LOGIC;
		data_out	:	OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
	);
END ENTITY integrator;

ARCHITECTURE behavior OF integrator IS

	SIGNAL reg_data_out	:	STD_LOGIC_VECTOR(9 DOWNTO 0);
	SIGNAL buf_data_out	:	STD_LOGIC_VECTOR(9 DOWNTO 0);
	
	BEGIN
	reg_data_out <= bit_in + buf_data_out;
	data_out <= reg_data_out;
	
	PROCESS(reset, clock)
		BEGIN
		IF (RISING_EDGE(clock)) THEN
			IF (reset = '1') THEN
				buf_data_out <= (OTHERS => '0');
			ELSE
				buf_data_out <= reg_data_out;
			END IF;
		END IF;
	END PROCESS;
END ARCHITECTURE behavior;

--------------------------------------------------------------------------------
-- decimator
-- works at original clock rate and decimates it by rate of 512
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY decimator IS
	GENERIC (
		decimation_rate	:	INTEGER RANGE 0 TO 1023 := 512
	);
	PORT (
		clock					:	IN STD_LOGIC;
		reset					:	IN STD_LOGIC;
		data_in				:	IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		decimated_clock	:	OUT STD_LOGIC;
		data_out				:	OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
	);
END ENTITY decimator;

ARCHITECTURE behavior OF decimator IS
	SIGNAL reg_data_out	:	STD_LOGIC_VECTOR(9 DOWNTO 0);
	SIGNAL counter			:	INTEGER RANGE 0 TO decimation_rate - 1;

	BEGIN
	data_out <= reg_data_out;
	PROCESS(reset, clock)
		BEGIN
		IF (RISING_EDGE(clock)) THEN
			IF (reset = '1') THEN
				decimated_clock <= '0';
				reg_data_out <= (OTHERS => '0');
				counter <= 0;
			ELSE
				IF (counter = (decimation_rate - 1)) THEN
					reg_data_out <= data_in;
					decimated_clock <= '1';
					counter <= 0;
				ELSE
					decimated_clock <= '0';
					counter <= counter + 1;
				END IF;
			END IF;
		END IF;
	END PROCESS;
END ARCHITECTURE behavior;

--------------------------------------------------------------------------------
-- comb
-- basically a fir filter with one negative feedfoward
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY comb IS
	PORT (
		clock		:	IN STD_LOGIC; -- decimated clock
		reset		:	IN STD_LOGIC;
		data_in	:	IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		data_out	:	OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
	);
END ENTITY comb;

ARCHITECTURE behavior OF comb IS

	SIGNAL buf_data_in	: STD_LOGIC_VECTOR(9 DOWNTO 0);
	
	BEGIN
	data_out <= data_in - buf_data_in;
	PROCESS (reset, clock)
		BEGIN
		IF (RISING_EDGE(clock)) THEN
			IF (reset = '1') THEN
				buf_data_in <= (OTHERS => '0');
			ELSE
				buf_data_in <= data_in;
			END IF;
		END IF;
	END PROCESS;
END ARCHITECTURE behavior;

I decided the output bit length by the fomula below.
Bout = N*log[2](R*M) + Bin
where N is the number of cascade, R is the rate of decimation, and M is number of delays in comb.


Best regards,

Yukihiro Hatagishi
 

The design should basically work.

It's not good to use a divided clock for the comb stage, it will bring up timing problems. Instead use decimated_clock as a clock enable for the fast clock.

Code: 
  IF (RISING_EDGE(clock)) THEN
    IF (decimated_clock = '1') THEN
      buf_data_in <= data_in;
    END IF;
  END IF;
 
Dear FvM,

Thank you for reply.


It seems to me that there is no problem with the design too...
I added "signed" so that compiler knew that 2's complement was used but the result did not change.

Though it is different from this topic, I am using LVDS_33 as a comparator and I am wondering if this is causing the trouble.
My question is, in LVDS if the positive input > negative input, is the output '1'?

Anyway, thanks for your advice about the timing clock.
I will change that way.


Best regards,

Yukihiro Hatagishi
 

Dear anddrival,

thanks for your reply.

I read through the CIC filter and I still don't get the reason why my design does not work...

The decimator (and therefore integrator too) works as I designed.

so stuck...
 

There are many solution : try to check each step by mark LED warnning on you algorihm that call "Stobing Signal" , and you should design circuit for noise also by make delay time for seqence signal.
 

I had found papers on two's complement noise consider calculation and for mathematician , system approch prefer , over more complexity.
 

Dear phongphang,


Thanks for your reply.

phongphanp said:
There are many solution : try to check each step by mark LED warnning on you algorihm that call "Stobing Signal" , and you should design circuit for noise also by make delay time for seqence signal.
Click to expand...
Can you tell me what "stobing signal" is??
I searched it on google but could not find any information of it.

Plus, I really want to read the paper about two's complement considering noise.
 

I don't exactly understand what problem do you want to solve now. Related to the the original question, you should better refer to "classical" CIC literature and known working CIC example designs from text books.
 

Dear phongphanp,


thanks for your reply.
I will try to find the paper you mentioned.

- - - Updated - - -

Dear FvM,


Thanks for your reply.


What I want to do is to realize delta sigma adc using FPGA.
To do that, I need a CIC filter for decimation filter.
Referring to the simulation result (got from ModelSim), all the output signals except from comb part is correct.
Only the comb output is wrong.

So what I want to do NOW is to let the comb part work correctly.
(In this case if the input is a continuous sine wave then the comb part should output discrete sine wave)


I read the one you mentioned.
But I still do not understand why the design does not work correctly...


Best regards,

Yukihiro Hatagishi
 

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