+ Post New Thread
Results 1 to 5 of 5
  1. #1
    Newbie level 2
    Points: 17, Level: 1

    Join Date
    Jul 2013
    Posts
    2
    Helped
    0 / 0
    Points
    17
    Level
    1

    latch warnings during synthesis of verilog code

    Hi all,

    Can you please help me to clear the following warnings....



    WARNIG:Xst:737 - Found 1-bit latch for signal <$old_fsm/1/fsm_enable_misr_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    WARNING:Xst:737 - Found 1-bit latch for signal <$old_fsm/1/fsm_enable_lfsr_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    WARNING:Xst:737 - Found 3-bit latch for signal <$old_fsm/1/fsm_NEXT_STATE_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.


    Code:

    module BIST_controller(input test_mode,input clk,input reset,input lfsr_ready,input bist_run,
    input bist_done,output enable_lfsr,output mux_sel,output enable_misr,
    output enable_misr_28_bit
    );

    //Internal FSM state declarations
    wire [1:0] NEXT_STATE;
    reg [1:0] PRES_STATE = 2'b00;

    //State encodings

    parameter s0 = 2'b00;//Normal mode
    parameter s1 = 2'b01;//Enable
    parameter s2 = 2'b10;//BIST_RUN
    parameter s3 = 2'b11;//BIST_DONE

    //Combinational logic

    function [5:0] fsm;

    input fsm_test_mode,fsm_reset,fsm_lfsr_ready,fsm_bist_ru n,fsm_bist_done;
    input [1:0] fsm_PRES_STATE;

    reg fsm_enable_lfsr;
    reg fsm_mux_sel,fsm_enable_misr,fsm_enable_misr_28_bit ;
    reg [1:0] fsm_NEXT_STATE;


    begin
    case (fsm_PRES_STATE)
    s0:// state = s0 -> Normal mode
    begin
    if((fsm_reset) && (fsm_test_mode) && (fsm_bist_done))
    begin
    fsm_enable_lfsr = 1'b1;
    fsm_mux_sel = 1'b1;
    fsm_NEXT_STATE = s1;
    end
    else
    begin
    fsm_enable_lfsr = 1'b0;
    fsm_mux_sel = 1'b0;
    fsm_NEXT_STATE = s0;
    fsm_enable_misr = 1'b0;
    fsm_enable_misr_28_bit = 1'b0;
    end
    end

    s1: //state s1 -> BIST Enable
    begin
    if(fsm_test_mode && fsm_reset && fsm_lfsr_ready)
    begin
    fsm_enable_misr = 1'b1;
    fsm_enable_misr_28_bit = 1'b1;
    fsm_NEXT_STATE = s2;
    end
    else
    begin
    fsm_enable_lfsr = 1'b0;
    fsm_mux_sel = 1'b0;
    fsm_enable_misr = 1'b0;
    fsm_enable_misr_28_bit = 1'b0;
    fsm_NEXT_STATE = s0;
    end
    end

    s2:// state s2 -> BIST_RUN
    begin
    if(fsm_test_mode && fsm_reset && !fsm_bist_run)
    begin
    fsm_NEXT_STATE = s3;
    end
    else if (fsm_bist_run)
    begin
    fsm_NEXT_STATE = s2;
    end
    else
    begin
    fsm_enable_lfsr = 1'b0;
    fsm_mux_sel = 1'b0;
    fsm_enable_misr = 1'b0;
    fsm_enable_misr_28_bit = 1'b0;
    fsm_NEXT_STATE = s0;
    end
    end
    s3: // state s3 -> BIST_DONE
    begin
    if (fsm_test_mode == 1'b1 && fsm_reset == 1'b1 && fsm_bist_done == 1'b1)
    begin

    fsm_NEXT_STATE = s0;
    fsm_enable_lfsr = 1'b0;
    fsm_mux_sel = 1'b0;
    fsm_enable_misr = 1'b0;
    fsm_enable_misr_28_bit = 1'b0;
    end
    else
    fsm_NEXT_STATE = s3;
    end


    endcase

    fsm = {fsm_mux_sel,fsm_enable_misr,fsm_enable_lfsr,fsm_e nable_misr_28_bit,fsm_NEXT_STATE};
    end
    endfunction

    //Reevaluate combinational logic

    assign {mux_sel,enable_misr,enable_lfsr,enable_misr_28_bi t,NEXT_STATE} = fsm(test_mode,reset,lfsr_ready,
    bist_run,bist_done,PRES_STATE);

    // clock the state flipflops
    // use synchronous reset
    always@(negedge clk or negedge reset)
    begin
    if(reset == 1'b0)
    PRES_STATE <= s0;
    else
    PRES_STATE <= NEXT_STATE;
    end
    endmodule

    •   AltAdvertisement

        
       

  2. #2
    Member level 1
    Points: 376, Level: 4

    Join Date
    Oct 2012
    Posts
    37
    Helped
    6 / 6
    Points
    376
    Level
    4

    Re: latch warnings during synthesis of verilog code

    Could't see the definition of fsm_NEXT_STATE_5, but for the other two (fsm_enable_misr_2 and fsm_enable_lfsr_3), you are forcing a constant value, which is implemented using latches.
    A workaround can be to make the synthetizer to use Flip-flops, so instead of having

    Code:
    if((fsm_reset) && (fsm_test_mode) && (fsm_bist_done))
    You can use a validation for edges (at least for one variable)

    Code:
    if((posedge fsm_reset) && (fsm_test_mode) && (fsm_bist_done))



    •   AltAdvertisement

        
       

  3. #3
    Newbie level 2
    Points: 17, Level: 1

    Join Date
    Jul 2013
    Posts
    2
    Helped
    0 / 0
    Points
    17
    Level
    1

    Re: latch warnings during synthesis of verilog code

    we can't use "posedge" with in if-else condition right....?



    •   AltAdvertisement

        
       

  4. #4
    Junior Member level 1
    Points: 131, Level: 1

    Join Date
    Aug 2013
    Location
    BANGALORE
    Posts
    17
    Helped
    3 / 3
    Points
    131
    Level
    1

    Re: latch warnings during synthesis of verilog code

    u can use posedge with if-else...no issue of using that but u must not use incomplete if-else block.....



  5. #5
    Junior Member level 1
    Points: 119, Level: 1

    Join Date
    Aug 2013
    Posts
    18
    Helped
    2 / 2
    Points
    119
    Level
    1

    Re: latch warnings during synthesis of verilog code

    In each state, all signals should be affected in the if and else branches.
    I checked your code quickly, sometimes you forget some signals.
    Example:
    s0:// state = s0 -> Normal mode
    begin
    if((fsm_reset) && (fsm_test_mode) && (fsm_bist_done))
    begin
    fsm_enable_lfsr = 1'b1;
    fsm_mux_sel = 1'b1;
    fsm_NEXT_STATE = s1;
    end
    else
    begin
    fsm_enable_lfsr = 1'b0;
    fsm_mux_sel = 1'b0;
    fsm_NEXT_STATE = s0;
    ////
    fsm_enable_misr = 1'b0;
    fsm_enable_misr_28_bit = 1'b0;
    ////
    end
    end

    These two signals were not mentioned in the if branch.
    I think this is the cause of the warning,
    You have to check your code.
    As I said all signals should be affected in if and else branches in all states.
    Regards



--[[ ]]--