What is the advantage of "writing netlist directly" over "drawing a schematic"?

What is the advantage of "writing netlist directly" over "drawing a schematic"?

Hi All:

When doing circuit simulation, one way is to write programs directly,
like
VS 1 0 DC 10V
R1 1 2 100
etc...

The other is to draw circuit in a schematic, then generate the netlist.

Re: the disadvantage of "writing netlist directly" over "drawing a schematic"?

I think writing a netlist manually is more error prone, as you can't find erroneous/wrong/missing connections easily. On a schematic you can run an ERC (Cādence: "check and save") which would show you at least some errors before you'd run the simulation. And seeing a schematic essentially facilitates an error search.

I'd say for ≤10 devices hand-writing a netlist is quite acceptable, but with higher complexity this starts to become more and more confusing, at least for a necessary error search.

Re: What is the advantage of "writing netlist directly" over "drawing a schematic"?

Writing a netlist has the advantage that you can easily incorporate subcircuits (opamp models) which are NOT yet included in your library.
Of course, this is possible also under schematics - however, for my opinion, more complicated since you must match (new) symbols and model description.

Re: What is the advantage of "writing netlist directly" over "drawing a schematic"?

Well, one advantage of the netlist-only way is that
you don't actually have to have schematic capture
software, its costs and/or learning curve.

Having spent many years in both modes, I feel that the
schematic driven design is worlds ahead in "throughput"
especially if you are doing on-the-fly topology fiddling.
But what is lost, is some of the as-you-go thought about
hierarchy and design parameters, etc. that sort of just
happens as you manually assign nodes and values, and
transcribe your paper sketch to (say) a working subcircuit
call.

Not that you can't apply disciplines and maintain order
in a schematic-driven design environment, but easy does
beget lazy.

The most significant advantage of schematic driven CAE
based design is that the same exact "circuit" that feeds
your simulations (electrical proof of design integrity) also
serves the backend as the verification schematic. That
drives out a whole bunch of opportunity for error there,
where it's deathly important. Fond memories of blue pencil
trace-by-trace checks, paper schematics vs Versatec 42"
layout plots tacked to the office wall... kinda amazing, in
retrospect, how little I screwed up in those days.

A lot of your answer depends on how important is, what
you are doing - and how costly the failure will be, vs the
up front expense to buy, and effort to learn, maximally
capable tools.