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Verilog A modelling of a current mirror (voltage controlled current source)

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mvj

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Hi,

I am trying to write a verilog A model for Voltage controlled current source.

module VCCS(p,n,pc,nc);
inout p,n;
input pc,nc;
electrical p,n,pc,nc;
parameter real gain=1;
branch (p,n) iSrc;

analog begin
I(iSrc) <+ gain*V(pc,nc);
end
endmodule


It works fine when there is a load connected to the current source but the simulation fails to converge when there is not load at the current source output. May I know if there is a way to identify is the current source terminal is floating and in this case set the current to zero.

Thanks a lot in advance,
mvj
 

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