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Comparing text files in Verilog

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Hi All,

Can anyone please tell me how to compare 2 text files in Verilog..?

Thanks !
 

Can you clarify, because this question is a bit vague.

But to strictly answer your question: open both files, then read byte from each and compare. Keep reading until end-of-file is reached or until first different byte is encountered.

Code: 
file_a = $fopenr("filename_a"); 
file_b = $fopenr("filename_b"); 

// etc
 
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