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Need to Know What is "False Path" with one or two examples

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amitjagtap

amitjagtap

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Hi all,
I wanted to know what is "False path" with one or two good examples/...
Thanks
 

a false path is one that would usually be analysed by the timing analyser, but for whatever reason, you dont want it to do it. An example would be signals that cross a clock domain boundary, or maybe something that you set once and doesnt change for a very long time, and having a "failing" path wont really have an effect on the design.
 

Imaging a single bit resynchronizer. ClkA clocks the source FF, and ClkB clocks the destination FFs. If the clocks are unrelated, eg 100.9876Mhz and 100.1234MHz, then the tools (ISE) will not analyze the path and will just report it as unconstrained. If the clocks are the same, then the tools will try to meet the 1-cycle constraint. The bad case is when the clocks both come from a PLL frequency synthesizer, eg 125MHz and 156.25MHz. The tools now have to meet a 1/5th cycle constraint (1.6ns).

In some cases, you don't want a false path -- for example the gray coded address bus of a fifo. There can't be more than one cycle of skew between the bits of this bus. In this case, a single rx clock cycle constraint prevents any significant skew.
 

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