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enc28j60 proteus simulation failed on CLKRDY check

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kalas

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Hi

I've made a simple design with a PIC18F452 and a ENC28J60.
I use CCS C 4.140 and the CCS TCPIP stack.

On simulation with Proteus 8 SP2, I've a problem in the MacInit () function, the check of CLKRDY bit always fail.

I can see spi signals from PIC with oscillo in the reading of ESTAT reg.

The strange thing is I can simulate the Explorer16 with PicTail exemple supplied with proteus with no trouble.

After several hours of search and tracking, I can't see what is wrong.

Some ideas will be welcome.
 

I've found, it's a timing issue.
When I compile my prog for 8MHz (HS Mode) and run the simulation at 8MHz, it's ok.
My original config, PLLx4 Mode and a Fosc=40 MHz, doesn't work.

Seems the ENC28J60 model from Proteus doesn't want the 10MHz SPI, like the old revison of this ic.
 

kalas said:
I've found, it's a timing issue.
When I compile my prog for 8MHz (HS Mode) and run the simulation at 8MHz, it's ok.
My original config, PLLx4 Mode and a Fosc=40 MHz, doesn't work.

Seems the ENC28J60 model from Proteus doesn't want the 10MHz SPI, like the old revison of this ic.
Click to expand...

Hi, im also trying out something on ethernet, please can you send your code and circuit diagram, it would realy be helpful to me. my mail is
oluwoleoyetoke@yahoo.com
 

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