Hang Zhang
Newbie level 1
I'm comparing two designs, and both designs are synthesized using both Cadence's RTL compiler and Synopsys' Design compiler
Same input netlists, same constraints, and same technology library.
Design A is faster then design B using RTL Compiler, but slower than B using Design compiler.
Any ideas why this would happen?
Same input netlists, same constraints, and same technology library.
Design A is faster then design B using RTL Compiler, but slower than B using Design compiler.
Any ideas why this would happen?