in verilog, combine edge trigger & blocking assignment

I am quite new with verilog, please share any idea you have.

in many articles, they only said that edge driven logic, logic in always @(posedge XXX), will be synthesis as flipflop. Should we say that logic using non-blocking assignment in the @(posedge XXX) procedural block will be synthesized as flipflop. for those using blocking assignment logics, they are still synthesized as com logic.

like this:
always @(posedge clk)
begin
a = b;
end

a will be synthesized as a buffer?

It will either be combinatorial logic (if a is only used within the process and only assigned before it is used), both logic and a register (if a is only used in the process, but is used before assignment and after assignment), or a register (a is only used before assignement). VHDL allows local variables to have blocking assignments, but these are explictly restricted to a single process.

However, the specific tool may not allow a to be used outside of the process unless very specific requirements are met. For example, if "a" is used to infer a multi-clock true dual-port ram in an FPGA.

This style is not generally reccomended because Verilog does not enforce an ordering between always block evaluation. This means that "a" cannot be used by any other logic that drives a register clocked by "clk" or any related clocks unless the signal is driving the clock port of said register only. In the former case, there is a chance that the signal will be inconsistently set by the driving process before being used by the other consuming processes.

The assignment to a would (may) happen if you have declared a as a reg. So, for the given statement "a" would be synthesized as a FlipFlop. Still a would be synthesized as FlipFlop for blocking as well as non-blocking assignments.