Timing difference between Write and Read cycles in MIG for DDR3

Hello all,

First of all, my specs are belo
Virttex-6, MIG for DDR3
Using Xilinx ISE
User Interface of MIG

Does any one knows the timing difference between write and read cycle.
I am issuing the Write commands consecutivly, and even that too with sets. i.e. 400 sets of 100 write commands.

After the last write command is issued, it means the data is organizaed in the 3D fashion by the algorithm I have decided. Now I want to fetch the data. But I cannot understnad for how many clock cycles(or in other words for how much time) should I wait to issue the first Read command. Note that read command is also issued consecutively, but this time somewhat like 400 sets of 100 commands each.

Unfortunately, I could not find this specific info in the data sheet.

Also, does the read command takes much longer time than the read command?

How much time difference should I give between two sets of read commands.



Waiting eagerly

In DDR3 datasheet check for read and write Latency....it will be mentioned in datasheet