Hi All,

I have imported a verilog design as a netlist view in cadence virtuoso, and now I am trying to cdl out for running LVS. I have a standard cell library, which has cells with symbol, layout and abstract views. On trying to CDLout I am getting an error that the cellviews are missing sim information which is indeed the case. Since there are hundreds of cells in the standard cell library, I don't want to hand edit the cdf info.

So my question is is there an easy way of creating symbols with the correct sim information from the standard cell library verilog netlist, lvs netlist or abstract etc.?