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Synthesis timing summary in Xilinx tool (ISE)

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asi123

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I'm getting the following timing summary from the synthesis:

Timing Summary:

Speed Grade: -1

Minimum period: 9.982ns (Maximum Frequency: 100.180MHz)
Minimum input arrival time before clock: 4.597ns
Maximum output required time after clock: 4.364ns
Maximum combinational path delay: 2.788ns

I want to improve that, is there a way to find the critical path and maybe buffer it up a bit?

I don't know what is the bottleneck...

Thanks a lot.

Assaf.
 

you'll have to look in detail at the timing. I cant remember the xilinx tools exactly but I know its there and should show you the slowest paths. Then you have to go back to the RTL to modify it - then re-simulate it to make sure it works with the new pipelining, then re-build it in ISE, and recheck timing.
 

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