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How to do the post-synthesis simulation?

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swgchlry

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I have synthesized my design using synopsys dc and got a .db file. But how can i do the post-synthesis simulation? Could I use nc-verilog to do this? If can't, which tool should i choose?
 

Why not! You can extract a netlist from your synthesized design. If your RTl or behavioral code was written by VHDL, you'd better extract a VHDL netlist because your testbenches are VHDL style. It is possible to simulate mixed language in most of simulator, but my experience shows that not to do it.
After nestlist extraction, you can simulate it by using any simulator. One of important points is about library which should be compiled before compiling your netlist. This library is delivered by manufacturer which includes gate level descriptions of different components.

Regards,
KH
 

Thanks for "khorram", your suggestion is helpful.
 

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