sainiparvesh
Newbie level 6
Hi,
For high speed circuits(>10Gbps) in tech. like 45nm or lower, we need to mirror current of the order of 3mA using programmable current steering DACs(which update at very low freq.) with the number of bits of the order of 7 or 8. Is it a good idea to have length of the main mirroring MOS of the order of 0.5um or even less with some cascade MOS with length 0.1um to save area? What else can be the smart ways to save area ?
For high speed circuits(>10Gbps) in tech. like 45nm or lower, we need to mirror current of the order of 3mA using programmable current steering DACs(which update at very low freq.) with the number of bits of the order of 7 or 8. Is it a good idea to have length of the main mirroring MOS of the order of 0.5um or even less with some cascade MOS with length 0.1um to save area? What else can be the smart ways to save area ?