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design compiler dynamic power estimation

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mehran1367

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hi all,

I want to see dynamic power in a huge vhdl code by considering the activity of signals. actually i want to add a few gates in the different paths. then i want to analyze the results.i think because my design is huge i cant do that. help
 

Salaam,

You can do it using synopsis tools by means of SAIF or VCD file. To do so, you should run an application on this VHDL code when it is running on Modelsim and dump switching activity and signal probabilities in a VCD or SAIF file. VCD file is rather easy but not applicable to large designs. How large is your code? Is it a processor?
 

salam :)

well, my component is a pipeline that I want to analyze the effect of dynamic power due to added gates to one of its stages. well I can create a component with just one of the stages of pipeline. but do you think is it possible to find out the effect of these gates on dynamic power of this stage?
 

It is possible, you should first synthesize the desired stage and then during the post-synthesis simulation (on modelsim or other similar tools) dump the vcd file. Power compiler of synopsis accepts VCD file and netlist and computes both leakage and dynamic power with respect to the running application.
 

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