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Tricky Question in VHDL??

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dcreddy1980

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hi...

entity test is
port(X : in std_logic;
clk : in std_logic;
Y : out std_logic);
end test;
architecture behaviour of test is
signal tmp : integer :=3;
signal clock period : time := 2 ns;
begin
Y <= X after tmp * clock period;
end behaviour;

u have to get the same behaviour as the above component does but not by using after statement in the code for delaying the inout data.
 

You just precede that assignment with wait statement for temp*period time.
 

add a counter in ur block.
 

is this correct ??

Code: 
entity test is
  port(X : in std_logic;
       clk : in std_logic;
       Y : out std_logic);
end test;
architecture behaviour of test is
  signal tmp : integer :=3;
  signal clock_period : time := 2 ns;
begin
  process
    begin
      wait for tmp * clock_period;
      Y <= X;  
    end process;
end behaviour;
 

If you mean to design some synthesizable statements instead of waiting statement, you should implement it by using a counter.
If your clock period is 2 ns, and you want to wait for (3*2 ns) 6 ns, you should add a counter which counts from 0 to 3. After receiving 3 on the counter, you can assign X to Y.

Regards,
KH
 

nand_gates, you forgot about sensitivity list for your process.
 

Tell me if I'm wrong, isn't wait statement not synthesisble? Probably I have use VHDL for a couple of months and the synthesis tools may have changed.
 

eziggurat said:
Tell me if I'm wrong, isn't wait statement not synthesisble? Probably I have use VHDL for a couple of months and the synthesis tools may have changed.
Click to expand...

Read again original question - it has nothing about synthesisable requirements. Just behaviour.

BTW, "wait" statement is synthesisable - of course, not the form "wait for time", but others, like "wait until condition".
 

opps, just browse it without looking at the last part :)
 

HI *,

1 2 3 4 5 6
-- -- -- -- -- --
| | | | | | | | | | | | (CLK)
--- -- -- -- -- -- --
----------------
| (X-input)
------------

-------------
|
---------------- (Y-output)

just take a look at the above figure...the statement Y <=X after 2 ns; will give u the waveform as above...if similarly ..if Y <= X after 4 ns is present then the o/p(Y should be LOW intially and would become HIGH at the "point 5" in reference to the CLK signal)...

i forgot to mention..the code should be a synthesizable one...
 

aji_vlsi said:
No, VHDL doesn't allow a prcoess with sensitivity list to have any wait statements inside.
Click to expand...

You are right, it was my mistake. Thank you for pointing this.
 

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