dcreddy1980
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hi...
entity test is
port(X : in std_logic;
clk : in std_logic;
Y : out std_logic);
end test;
architecture behaviour of test is
signal tmp : integer :=3;
signal clock period : time := 2 ns;
begin
Y <= X after tmp * clock period;
end behaviour;
u have to get the same behaviour as the above component does but not by using after statement in the code for delaying the inout data.
entity test is
port(X : in std_logic;
clk : in std_logic;
Y : out std_logic);
end test;
architecture behaviour of test is
signal tmp : integer :=3;
signal clock period : time := 2 ns;
begin
Y <= X after tmp * clock period;
end behaviour;
u have to get the same behaviour as the above component does but not by using after statement in the code for delaying the inout data.