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  1. #1
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    Tricky Question in VHDL??

    hi...

    entity test is
    port(X : in std_logic;
    clk : in std_logic;
    Y : out std_logic);
    end test;
    architecture behaviour of test is
    signal tmp : integer :=3;
    signal clock period : time := 2 ns;
    begin
    Y <= X after tmp * clock period;
    end behaviour;

    u have to get the same behaviour as the above component does but not by using after statement in the code for delaying the inout data.

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    Re: Tricky Question in VHDL??

    You just precede that assignment with wait statement for temp*period time.



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  3. #3
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    Tricky Question in VHDL??

    add a counter in ur block.



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    Re: Tricky Question in VHDL??

    is this correct ??

    Code:
    entity test is
      port(X : in std_logic;
           clk : in std_logic;
           Y : out std_logic);
    end test;
    architecture behaviour of test is
      signal tmp : integer :=3;
      signal clock_period : time := 2 ns;
    begin
      process
        begin
          wait for tmp * clock_period;
          Y <= X;  
        end process;
    end behaviour;



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    Re: Tricky Question in VHDL??

    If you mean to design some synthesizable statements instead of waiting statement, you should implement it by using a counter.
    If your clock period is 2 ns, and you want to wait for (3*2 ns) 6 ns, you should add a counter which counts from 0 to 3. After receiving 3 on the counter, you can assign X to Y.

    Regards,
    KH



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  6. #6
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    Tricky Question in VHDL??

    nand_gates, you forgot about sensitivity list for your process.



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    Re: Tricky Question in VHDL??

    Tell me if I'm wrong, isn't wait statement not synthesisble? Probably I have use VHDL for a couple of months and the synthesis tools may have changed.



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    Re: Tricky Question in VHDL??

    Quote Originally Posted by eziggurat
    Tell me if I'm wrong, isn't wait statement not synthesisble? Probably I have use VHDL for a couple of months and the synthesis tools may have changed.
    Read again original question - it has nothing about synthesisable requirements. Just behaviour.

    BTW, "wait" statement is synthesisable - of course, not the form "wait for time", but others, like "wait until condition".



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    Re: Tricky Question in VHDL??

    opps, just browse it without looking at the last part :)



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    Re: Tricky Question in VHDL??

    Quote Originally Posted by Ace-X
    nand_gates, you forgot about sensitivity list for your process.
    No, VHDL doesn't allow a prcoess with sensitivity list to have any wait statements inside.

    Ajeetha
    http://www.noveldv.com



  11. #11
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    Tricky Question in VHDL??

    HI *,

    1 2 3 4 5 6
    -- -- -- -- -- --
    | | | | | | | | | | | | (CLK)
    --- -- -- -- -- -- --
    ----------------
    | (X-input)
    ------------

    -------------
    |
    ---------------- (Y-output)

    just take a look at the above figure...the statement Y <=X after 2 ns; will give u the waveform as above...if similarly ..if Y <= X after 4 ns is present then the o/p(Y should be LOW intially and would become HIGH at the "point 5" in reference to the CLK signal)...

    i forgot to mention..the code should be a synthesizable one...



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  12. #12
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    Re: Tricky Question in VHDL??

    Quote Originally Posted by aji_vlsi
    No, VHDL doesn't allow a prcoess with sensitivity list to have any wait statements inside.
    You are right, it was my mistake. Thank you for pointing this.



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