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How to run synthesized simulation ..

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NATHANHSIEH

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ncsim manual

Hi!!!
Could anyone tell me how to run synthesized simulation
(simulation tools is Cadence's nc-sim & compiler tools is Synopsys's DC)??
Which files to need??? *.sdf or *.v???
Could anyone to provide method for me ??
If you have any suggestion please let me more clear...
 

netlist simulation zero_delay_mode

netlist (*.v) + sdf file + library (*.v)
 

Re: How to run synthesized simulation ......

use system task $sdf_annotate to annotate timing info. in gate level simulation.
 

Re: How to run synthesized simulation ......

For GAte sim,
pleas eget netlist and *.sdf file , and do by ncsim
 

almost no difference between rtl sim and gate-level sim
 

*in your test bench top_sim.v (for example)
*add the following in your test bench .v:

initial $sdf_annotate(top_design.sdf,utop_design);
----------------------------------------------------------
*in your .f file, top_sim.f (for example)

-v $libry_path/library_model.v

top_sim.v

top_design_gate.v // synthesized netlist
----------------------------------------------------------
*run simulation using ncverilog

ncverilog -f top_sim.f
----------------------------------------------------------

when running simulation to sdf annotate stage, you may face some sdf back-annotate problem need to solve...........
 

You actually do not need to the SDF file for gate level simulation, if you don't tend to do timing verification by running gate sim. Turn off the dealy by adding "zero_delay_mode", (I can't remember very clearly, check the NCSIM manual). Or, simply slow down the clock.
 

just after synthesis, you can run simulation on netlist + library verilog modek with
zero delay mode.
of course, you can also write a sdf file in DC, and run simulation with the sdf file.
after APR, you can get accurate sdf file, it means you can run post-simulaiton.
 

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