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Question about Altera Avalon bus slave fundmental transfer

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sidir

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I am using Altera Nios and has question about Avalon bus slave fundmental transfer. In Avalon bus specification, slave fundmental read transfers data from peripheral to bus module immediately after "chipselect" and "read" signals are asserted. Does this mean the read transfer need no "clk" signal? I plan to design the peripheral as: seeing "chipselect" and "read" both = '1', then output "readdata", otherwise register the value of "readdata". No synchronization to "clk". Will it be correct? Thanks!
 

Question about @ltera Avalon bus slave fundmental transfer

Hello sidir,

The Avalon bus is a fully synchronous bus so it is necessary to synchronize all operations to the rising edge of the clock. More information about the Avalon bus can found under: **broken link removed**

Another good source for information about this topic would be the Nios Discussion Forum: **broken link removed**


Bye,
cube007
 

Question about @ltera Avalon bus slave fundmental transfer

Thank you cube007!
 

Question about @ltera Avalon bus slave fundmental transfer

Hello sidir,

You are new at this forum. Please don’t post only for thanking someone. Use the “Helped me bottom” (h**p://) instead.

Bye,
cube007
 

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    sidir

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Question about @ltera Avalon bus slave fundmental transfer

Hi cube007,

I think if avalon slave issue readdata at clk's rising edge, avalon master could only latch the data at next clock cycle, it seems to be a latency read transfer. Maybe we can try to output readdata at falling edge of clk, then avalon master can latch the data at the following rising edge of the same clock cycle.
 

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