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    ASIC Physical design

    Hi friends can anyone explain me how to calculate core ring width and metal stripe width

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    Re: ASIC Physical design

    Usually, a min. dimensions p+ on p-substrate guard ring with a single row of min. spaced contacts between p+ & metal1 connected to VSS/GND should do:



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    Re: ASIC Physical design

    If you're talking about the power bussing for the logic core,
    it goes something like

    1) What is the lower voltage bound of timing-model validity

    2) What is your minimum supply?

    3) If you're not already screwed, this is Vdrop(max) across
    the sum of leadframe, bondwire and on-chip distribution
    bussing. Leadframe and bondwire (or bump, or whatever)
    should be knowable. These have imposed on them the
    additional burden of I/O DC and switching currents and
    dI/dt. Quantify those, worst case (#, PVT) and take
    away that from Vdrop(max).

    4) Still not screwed? Then figure your core quasi-DC
    (Cvf rolled up) current and any major-core-switching-
    event which is probably well higher. Major event dI/dt
    speaks to L which won't respond too much to sizing,
    but a lot to length of run and parallelism of power feed.
    quasi-DC goes to ohmic drops which do care about
    sizing, and to electromigration reliability (current density).
    In any case you need the W to make your EM rule, but
    the major-switching-event is likely to dominate. Anyway,
    from Vdrop residual and the quasi-DC current you can
    figure an R target, from major-event peak Icore you can
    figure another, and so on. But getting to a power rail
    W requires that you have an architecture (parallel feeds
    and where they come in, whether they are strapped in
    thicker higher metal, end-fed vs center fed, all that stuff)
    and ability to figure current partitioning and solve for
    the worst case core drop.

    The days of doing that by hand, ended long ago; with the
    big grids of mega-gate logic a power integrity tool is a whole
    lot more attractive (if you're not the one paying).

    When doing the tens-of-Kgates type custom logic that I've
    had to, I just make the "core stripes" as fat as can stay with
    minimum spacing (not wide-metal rules) and the rings, as fat
    as keeps me out of metal slotting. Embedding a lot of plate
    capacitance in the bus structures and gate-ox caps as array
    "spacers" helps knock down the major-switching problem a lot.
    But I can't say as I've tried to figure rail-span-collapse in a
    couple of decades, scientifically.



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