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    Problem with designing an OTA using 90nm technology

    I have a major problem and i am out of ideas so any suggestions will be great....
    below is the image of the circuit i am trying to simulate: its for an OTA using 90nm technology: the requirements are
    1. high linearity 2. high gain 3.low noise... the only difference in my circuit from the one in the image is that i am using all PMOSs

    1) http://obrazki.elektroda.pl/3237069900_1362096134.jpg

    This the linearity curve i am getting:
    2)http://obrazki.elektroda.pl/3452880100_1362096357.jpg

    and i am getting a very bad curve for the gain as shown below:
    http://obrazki.elektroda.pl/7154024700_1362096444.jpg

    I chose the Ibias to be 4uA... the aspect ratios are as follows:

    for M1&M2 are W=8.769n L=90nm
    for M3 to M6 are W=5.35u L=180nm
    for M7 & M8 are W=2.67u L=180nm
    for M9 & M10 are W=8.769nm L=90nm
    for Mcascp are W=450n L=1.35u
    for Mcascn are W=7.35u L=1.35u

    I dnt know whats the problem... the curve for the linearity looks ok.. but the gain is so bad.. i dont knw how to fix this from where to do i start ... so any suggestions are highly appreciated..
    Thanks in advance

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  2. #2
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    Re: Problem with designing an OTA using 90nm technology

    I would expect bad linearity if you are using all pfets, they will not work well with gates near supplies... why arent you using traditional cmos design ?



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  3. #3
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    Re: Problem with designing an OTA using 90nm technology

    Please pay attention to forum rules regarding cross postings. You already started a same topic thread. https://www.edaboard.com/thread281550.html



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  4. #4
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    Re: Problem with designing an OTA using 90nm technology

    even when using traditional CMOS design...the response is even worse for both linearity and gain

    - - - Updated - - -

    i didnt mean to cross post.. i am new to the forum... my other post i was asking about smthg else and then one of the members asked to to elaborate... i apologize for not pay attention to that



  5. #5
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    Re: Problem with designing an OTA using 90nm technology

    Hi ashyma

    Using longer L you will get higher gain. I have simple opam attached for you as reference: Gain ~65db, phase margin 90deg




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  6. #6
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    Re: Problem with designing an OTA using 90nm technology

    I do not design in 90nm but i cant understand the increase of gate leads to increase of gain.. it leads to decrease in power via leakage current i guess. but increases caps at all nodes, slowing circuits down and if holding the W and current constant while reducing L will reduce your gm and should reduce your gain right? Maybe I am having a brain fart from lack of caffeine this morning.
    -Pb



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