Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Setup time failure detection

Status
Not open for further replies.
R

rogger123

Advanced Member level 4
Joined
Apr 9, 2003
Messages
112
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
1,232
hi,
Can someone give me some methods to identify setup time violations after the chip is fabricated... any techniques to know if it is a setup or a hold time violation??
 

rogger123 said:
hi,
Can someone give me some methods to identify setup time violations after the chip is fabricated... any techniques to know if it is a setup or a hold time violation??
Click to expand...

1. Setup time violation:
Slow down your chip clock freq., if OK, then it is setup time violation.
2. If slow down still failed -> hold time violation.

But some time it is due to power problem, so, raise up or down your chip working
voltage can give you idea about failure reason.
 

hi, rogger123
Why not to check the STA with your netlist after P&R?
 

Hi,
Is there any way to locate a setup time violation in the chip(after the chip is fabricated)... meaning identify the flip flop which had the setup time violation?
 

rogger123 said:
Hi,
Is there any way to locate a setup time violation in the chip(after the chip is fabricated)... meaning identify the flip flop which had the setup time violation?
Click to expand...
Usually, when you create your design, there should be lots of debug bus or status check points, you can check which block failed in running chip.
It's really not easy to make sure which DFF has violation.
 

abner said:
rogger123 said:
hi,
Can someone give me some methods to identify setup time violations after the chip is fabricated... any techniques to know if it is a setup or a hold time violation??
Click to expand...

1. Setup time violation:
Slow down your chip clock freq., if OK, then it is setup time violation.
2. If slow down still failed -> hold time violation.

But some time it is due to power problem, so, raise up or down your chip working
voltage can give you idea about failure reason.
Click to expand...
If there are realy some hold violations, the silicon will be a garbage.:)
 

in real test process , setup and hold time check are all standard function of ATE.
you can inquire some test engineer
 

you must use PT to do STA first,
after fabricated,it's about test process;
 

1. get star rc file and rerun the STA
2. slow down your work Frequency and test again
3. increase you chip temp and check if there are hold time failure

but for most situation, hold time failure couldn't let whole chip failure.
 

Please do STA use Prime time,
then all violations may gone
 

do testing on both the fast parts & slow parts.
 

Yes , and Use "minmax case analysis" ..in primetime..
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top