+ Post New Thread
Results 1 to 6 of 6
  1. #1
    Advanced Member level 5
    Points: 24,282, Level: 37
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,656
    Helped
    1032 / 1032
    Points
    24,282
    Level
    37

    Can I do this in VHDL?

    Maybe I'm trying to do something I can't, but it seems like I should be able to.

    Here's a snippet:

    Code:
    signal big:std_logic_vector(15 downto 0);
    signal little:std_logic_vector(3 downto 0);
    .
    .
    .
    little<=(big-x"0010")(3 downto 0);
    This is part of a testbench I'm using in Active-HDL, and it doesn't like the assignment. The error I get says it wants a ";" before the "(3 downto 0)". If I eliminate the "(3 downto 0)", it compiles ok, but then fails at runtime (as would be expected).

    Any thoughts, guys?

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 5
    Points: 37,911, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,874
    Helped
    2019 / 2019
    Points
    37,911
    Level
    47

    Re: Can I do this in VHDL?

    Hmm, I always thought you could, but apparently not.

    However, you can slice a function return, rather than an operator

    Code VHDL - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    
    library ieee;
    use ieee.std_logic_1164.all;
    --use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all;
     
    entity test is
    end entity test;
     
    architecture rtl of test is
      signal a : signed(15 downto 0);
      signal b : signed(3 downto 0);
      
      function minus(a : signed) return signed is
      begin
          return a - 1;
      end function;
      
    begin
     
      b <= minus(a)(3 downto 0);
     
    end rtl;


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  3. #3
    Advanced Member level 5
    Points: 24,282, Level: 37
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,656
    Helped
    1032 / 1032
    Points
    24,282
    Level
    37

    Re: Can I do this in VHDL?

    Thanks Tricky

    Just thought it would be nice if it worked MY way.

    This might actually be a problem with the active-HDL compiler. Since it's a testbench, I haven't tried to synthesize it. I might just do a test to see if it synthesizes.



    •   AltAdvertisement

        
       

  4. #4
    Advanced Member level 5
    Points: 37,911, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,874
    Helped
    2019 / 2019
    Points
    37,911
    Level
    47

    Re: Can I do this in VHDL?

    It failed in modelsim for me, so I assume its a language thing.



  5. #5
    Advanced Member level 5
    Points: 24,282, Level: 37
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,656
    Helped
    1032 / 1032
    Points
    24,282
    Level
    37

    Re: Can I do this in VHDL?

    Well, that does it. I'm making my own HDL.



    •   AltAdvertisement

        
       

  6. #6
    Advanced Member level 5
    Points: 37,911, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,874
    Helped
    2019 / 2019
    Points
    37,911
    Level
    47

    Re: Can I do this in VHDL?

    Haha
    First try AHDL then get really mad...



--[[ ]]--