davyzhu
Advanced Member level 1
I have read a techxclusive from Xilinx named "Timing closure", it suggest that we should 'Use internal three-state buffers to replace large multiplexers', because 'Virtex based FPGAs use dedicated AND-OR logic to implement three-state buffers', and 'Can reduce multiplexer delays'.
I was told that internal 3-state should be avoid when design asic, but why the xilinx suggestion? Anyone have the experience? And I am curious to know how to implement 3-state in AND-OR logic?
DAVY
I was told that internal 3-state should be avoid when design asic, but why the xilinx suggestion? Anyone have the experience? And I am curious to know how to implement 3-state in AND-OR logic?
DAVY