Declaring 2 RAMs together in Verilog?

hassanzia · Jan 27, 2013

Is there a difference between the following two statements?

Code:

reg [7:0] a,b [0:1023];

AND

Code:

reg [7:0] a [0:1023];
reg [7:0] b [0:1023];

I'm just curious because declaring them together caused my code to go haywire, whilst declaring them separately solved everything!

permute · Jan 28, 2013

possibly:

Code:

reg [7:0] a [0:1023], b [0:1023];

Though I'm not sure. I use marker based code folding (in vim/emac/etc...) and just hide the declarations.