Looking for documents on SystemVerilog and SystemC

SystemVerilog n' SystemC

Are there any decient docs/nfo's on using either of these.

I have seen the systemverilog spec.. but its not the most friendly document..

as for systemC.. i haven't seen anything

jelydonut

Re: SystemVerilog n' SystemC

dear jelydonut

you can join (free) www.systemc.org.

Then you can get the source distribution with two friendly intros to SystemC (the UserGuide and another doc I can't remember). Also the SystemC LRM is consistent and very-very friendly for a standard (standards get real tight*ss most of the times).

What makes me furious with SystemVerilog is not the language itself. I haven't tried it (i know VHDL, Verilog and some SystemC). It is the fact that SystemVerilog is just a VHDL ripoff that annoys me. It is NOT DECENT TO CALL IT SYSTEMVERILOG. IT SHOULD BE CALLED SYSTEMVHDL. Verilog always had the strongest support from industry. Due to the fact that you need simpler parsers for it. And built smaller descriptions. Otherwise it has laughable type checking, and misses a lot of the VHDL features.

the_penetrator©

Re: SystemVerilog n' SystemC

SystemC and SystemVerilog
Maybe they can work together.

SystemVerilog n' SystemC

you can get systemC book In the upload download section.

SystemVerilog n' SystemC

system design with systemc is a good book