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  1. #1
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    gate level modelling of fir filter in verilog

    hi everyone,
    my seminar uses an FIR filter that has reduced number of multipliers. so my code need to consider the structure. do i need to code it in gate level?
    the filter coeffficients obtained from matlab is 64 bit. how can i convert it to lower bits or how can i directly use them as signed numbers in verilog?
    expecting your help and thanking you....

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  2. #2
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    Re: gate level modelling of fir filter in verilog

    The problem hasn't to do with gate level, I think. It's just about fixed point arithmetic. Normally, you'll want to simulate the effect of coefficient length reduction in Matlab and define the exact fixed point filter represention for the final implementation.


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