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Critical path (Xilinx ISE)

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spman

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Hi

How can find the critical path that is preventing clock constraint to be met? I use Xilinx ISE.
 

You have all of your delays in synthesis report.
 

moottii said:
You have all of your delays in synthesis report.
Click to expand...

Synthesis report or place and route report? I found information about delays in place and route report. But I don't know how it is useful. How should exploit it?

Thanks
 

There is a small part in synthesis report called "Timing Report".
You can find them there.
 

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