+ Post New Thread
Results 1 to 8 of 8
  1. #1
    Advanced Member level 3
    Points: 3,827, Level: 14

    Join Date
    Oct 2011
    Posts
    772
    Helped
    5 / 5
    Points
    3,827
    Level
    14

    example of path for multi clock design

    Can anyone please provide example of paths that are not treated as false paths although they are path crossing from one clock domain to another clock domain?

    •   AltAdvertisment

        
       

  2. #2
    Junior Member level 1
    Points: 91, Level: 1

    Join Date
    Dec 2012
    Location
    CHENG DU, China
    Posts
    15
    Helped
    5 / 5
    Points
    91
    Level
    1

    Re: example of path for multi clock design

    Data within DDR PHY.
    Need shift the DQs to capture DQ (named as dq_reg), then, dq_reg will be transfered to clock domian in the chip (this can't be a flase path while transfer between 2 clock domains).



  3. #3
    Advanced Member level 3
    Points: 3,827, Level: 14

    Join Date
    Oct 2011
    Posts
    772
    Helped
    5 / 5
    Points
    3,827
    Level
    14

    Re: example of path for multi clock design

    Quote Originally Posted by asic_service View Post
    Data within DDR PHY.
    Need shift the DQs to capture DQ (named as dq_reg), then, dq_reg will be transfered to clock domian in the chip (this can't be a false path while transfer between 2 clock domains).
    Can you please elaborate the path in detail with an diagram so that what you want to say is understood well? How does the path look like? What kind of combinational logic will be there in that path? Why is it necessary to check the timing of such a path such that false path cannot be set?



    •   AltAdvertisment

        
       

  4. #4
    Member level 5
    Points: 1,144, Level: 7

    Join Date
    Jun 2011
    Posts
    88
    Helped
    6 / 6
    Points
    1,144
    Level
    7

    Re: example of path for multi clock design

    in clock domain crossing, you set false path for hold while doing synthesis because two clocks are asynchronous and timing cannot checked.

    But you set set_max_delay and set_min_delay on these paths. so that data should reach after specified delay.



  5. #5
    Full Member level 3
    Points: 1,700, Level: 9

    Join Date
    Dec 2011
    Posts
    173
    Helped
    69 / 69
    Points
    1,700
    Level
    9

    Re: example of path for multi clock design

    Hai sunray,

    Please note it may be derived clock..
    *******Hope this may help u..Have fun*****************

    ********************VJ R15***************************

    "When the World says give up I will try one more time"



    •   AltAdvertisment

        
       

  6. #6
    Advanced Member level 3
    Points: 3,827, Level: 14

    Join Date
    Oct 2011
    Posts
    772
    Helped
    5 / 5
    Points
    3,827
    Level
    14

    Re: example of path for multi clock design

    Quote Originally Posted by rocking_vlsi View Post
    in clock domain crossing, you set false path for hold while doing synthesis because two clocks are asynchronous and timing cannot checked.

    But you set set_max_delay and set_min_delay on these paths. so that data should reach after specified delay.
    How does it answer my question?

    - - - Updated - - -

    Quote Originally Posted by vijayR15 View Post
    Hai sunray,

    Please note it may be derived clock..
    I am asking example of path. How does your reply answer my question?



  7. #7
    Full Member level 4
    Points: 1,182, Level: 7

    Join Date
    Oct 2012
    Posts
    200
    Helped
    20 / 20
    Points
    1,182
    Level
    7

    Re: example of path for multi clock design

    Lets say there are two state machines. 1st state machine runs on clock1 and 2nd state machine runs on clock 2. In design after 1ststate machine is completed you have to move to 2nd state machine. You have to pass a signal from 1st state machine to inform 2nd state machine to start.

    Tell me whether it answered your question or not ?



  8. #8
    Full Member level 6
    Points: 1,708, Level: 9
    ads_ee's Avatar
    Join Date
    Oct 2012
    Location
    San Diego
    Posts
    328
    Helped
    88 / 88
    Points
    1,708
    Level
    9

    Re: example of path for multi clock design

    sun_ray,

    Here is an example...

    Attachment 86714

    As clk_1x and clk_2x are phase locked, the setup/hold time between Reg 1 and Reg 2 is not a false path. Place and route tools should be able to compensate for any clock skew between the two clock domains to meet both setup and hold time.

    Yes, you could treat it as asynchronous, but that would then require synchronization registers at the output of Reg 1 clocked on clk_2x. These synchronization registers wouldn't be doing much besides compensating for skew introduced due to a false_path placed on the clock crossing. Depending on the clock skew involved the first synchronization register could experience continuous metastable events if the skew results in the data arriving at the syncrhonization register coincident with the clock edge. So by using a false path in this case we might actually make things more likely to go metastable.
    Last edited by ads_ee; 7th February 2013 at 19:10.



--[[ ]]--