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Verilog Testbench to monitor signal relationship

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aspirinnnnn

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I am currently working on a CMOS Image Sensor controller. this controller has to give a huge control signals to the ADC and Pixel array. those signals has its fixed relationship like:
a is pull up high for 10 clock,then pull down for 15 clock and .....
b is pull up high one clock behind the a ,and then stay high for xxx clock
c is ........

how do i achieve auto automatically test in testbench, thanks for any helps
 

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